在恩智浦官网文档 《i.MX RT Hardware Development Guide for the MIMXRT1050/MIMXRT1060 Processor》 里对上电时序做了如下严格规定,其中最常发生问题的地方就是有效 DCDC_PSWITCH 和 DCDC_IN 之间至少 1ms 的延时(以 DCDC_IN 稳定在 3V 为时间起点,以 DCDC_PSWITCH 上升到 1.5V 为时间终点),如果不满足这个 1ms 延时要求,内部 DCDC 模块则可能会启动失败,无法正常输出电压给内核(DCDC_LP 脚)。
• The VDD_SNVS_IN supply must be turned on before any other power supply or connected (shorted) with the VDD_HIGH_IN supply. • If a coin-cell battery is used to power VDD_SNVS_IN, ensure that it is connected before any other supply is switched on. • An RC delay circuit is recommended for providing the delay between DCDC_IN stable and DCDC_PSWITCH. The total RC delay should be 5-15 ms. • DCDC_IN must reach a minimum 3.0 V within 0.3 x RC. • The delay from DCDC_IN stable at 3.0 V min to DCDC_PSWITCH reaching 0.5 x DCDC_IN (1.5 V) must be at least 1 ms. • The power-up slew rate specification for other power domains is 360 V/s – 36k V/s. • POR_B must be held low during the entire power up sequence