第一天课程：2017年7月31日（09:00-17:00）
1、PLL拓扑的基本概念-Basic Concepts of PLL Topologies
锁相环拓扑的基本定义和概念，PLL拓扑结构的频率特性、稳定性，分数N合成器简介。
Basic definitions and concepts of phase locked loop topologies. Frequency behavior, stability and settling of PLL topologies. Introduction of fractional N synthesizers.
2、CMOS预分频器 & 高级环路滤波器-CMOS Prescalers & Advanced Loop Filters
详细介绍高速 CMOS预分频器，双模预分频器和相位切换架构等高阶电路技术。相位检测器和环路滤波器对全集成PLL合成器的限制和要求。针对DCS1800应用的集成合成器的案例研究。
High-speed CMOS prescaler, dual modulus prescaler and advanced circuit techniques, such as phase switching architectures, are discussed in detail. The limitations and requirements of the phase detector and loop filter towards fully integrated PLL synthesizers are discussed. A case study of an integrated synthesizer for DCS1800 applications is analyzed.
3、集成VCOs和合成器（上部和下部）-Integrated VCOs and Synthesizers (part1 and part 2)
电路的基本原理，CMOS VCO电路的螺旋电感和变容二极管的版图和设计问题，环路滤波器和VCO噪声对PLL合成器的相位噪声特性的影响，CMOS技术中全集成合成器的设计实例。
Fundamentals and principles of VCO circuits. Lay-out and design issues of spiral inductors and varactors for CMOS VCO circuits. Effect of loop filter and VCO noise on phase noise behavior of PLL synthesizers. design examples of fully integrated synthesizers in CMOS technologies.
第二天课程：2017年8月1日（09:00-17:00）
4、晶体振荡器-Crystal Oscillators
晶振的基本设计原理，首先讨论‘split’分析方法，基于这一原理，讨论晶体振荡器的设计过程，不同的拓扑结构，如Pierce、Colpitts、Santos、单引脚和基于反相器的振荡器以及PSRR的影响。
The basic principles of crystal oscillators and their designs are studied. First the 'split' analysis will be discussed, and based on this principle the design procedure of crystal oscillators is discussed. Different topologies, such as Pierce, Colpitts, Santos, single -pin and inverter-based oscillators and the effect of PSRR are described.
5、IC干扰效应: 噪声和耦合-Interference Aspects in IC: Noise and Coupling
分析不同噪声源及其对耦合效应的影响，还将讨论数字和模拟电路噪声产生架构的两个案例，钉扎效应，衬底效应，引线键合及其他设计规则。
Different sources and their impact on coupling effects are analyzed. Both examples of digital and analog circuit noise generating structures are presented. A brief discussion of pinning strategy and substrate effects are discussed. Design rules and bondwire effects are investigated.
6、IC干扰效应：匹配和CMPR-Interference Aspects in IC: Matching and CMRR
为了减小这种效应，通常采用高PSRR的差分结构和电路，然而这同样要求具有高共模抑制比和对称的拓扑电路。这些参数与原理图和版图的匹配特性密切相关，我们将分析CMRR和匹配性能的关系，然后思考版图布局的一些因素。
To reduce to effect differential structures and circuits towards high PSRR a commonly used. This however requires circuits with high CMRR, PSRR and symmetrical topologies. Those are strongly related to the matching properties of the schematic and lay-out. for that matching performances are analyzed followed by CMRR relationships. Finally some lay-out considerations are presented.
7、IC干扰效应: PSRR-Interference Aspects in IC: PSRR
讨论通过电源对射频电路进行集成的一些干扰效应，以及基本模块（运放）中高电源抑制比的设计技术。
Some interference effects in integrating RF circuits via power supply are addressed and discussed. Design techniques for high power supply rejection ratio in basic analog building blocks (opamps) are studied.
