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会议全称：International Conference on Computer Design
录用率：2021年34.55%
CCF分级：计算机体系结构/并行与分布计算/存储系统B
截稿时间：2024/5/5
录用通知时间：2024/8/1
官网链接：
https://www.
iccd-conf.com/Home.html
征稿范围：
Track 1. Computing Systems:
System architecture; System support for multi/many cores, co-processors, and accelerators; System support for security, reliability, and energy efficiency and proportionality; Virtual memory; System support for emerging technologies, including NVM, quantum, neuromorphic, bio-inspired computing, machine learning and artificial intelligence applications; Storage systems for data center and cloud/edge computing, high-performance computing (HPC), exascale system, and serverless computing.
Track 2. Software Architectures, Compilers, and Tool Chains:
Software architectures, compilers, programming language/model, firmware, OS, hypervisor, runtime design, and co-design for embedded/real-time systems; Middleware for embedded systems, including resource-awareness, reconfiguration, energy/power management; compiler support for enhanced debugging, profiling, and traceability.
Track 3. Hardware Architectures:
Microarchitecture design techniques for single-threaded and multi/many-core processors, such as instruction-level parallelism, pipelining, caches, branch prediction, multithreading, and networks-on-chip; Techniques for low-power, secure, and reliable processor architectures; Hardware acceleration for emerging applications including NVM, quantum, neuromorphic, bio-inspired; Hardware support for processor virtualization; Real-life design challenges: case studies, tradeoffs, retrospectives.
Track 4. Test, Verification, and Security:
Design error debug and diagnosis; Fault modeling; Fault simulation and ATPG; Analog/RF testing; Statistical test methods; Large volume yield analysis and learning; Fault tolerance; DFT and BIST; Functional, transaction-level, RTL, and gate-level modeling and verification of hardware designs; Equivalence checking, property checking, and theorem proving; Constrained-random test generation; High-level design and SoC validation; Hardware security primitives and methodologies; Side-channel analysis, attacks and mitigations for processors and accelerators; Interaction between test, security and trust.
Track 5. Electronic Design Automation:
System-level design and synthesis; High-level, logic, and physical synthesis; Analysis and optimization of timing, power, variability/yield, temperature, and noise; Physical design, including partitioning, floorplanning, placement, and routing; Clock tree synthesis; Verification methods at different levels of the EDA flow; Tools for multiple-clock domains, asynchronous, and mixed-timing methodologies; CAD support for accelerators, FPGAs, SoCs, ASICs, NoC, and general-purpose processors; CAD for manufacturing, test, verification, and security; Tools and design methods for emerging technologies (photonics, MEMS, spintronics, nano, quantum); interaction of EDA and AI/ML.
