2025 Chiplet Summit 会议资料分享

Pre-Con A: Chiplet Basics (Pre-Conference Tutorials    Track)

Multi-Die    Design from Architecture Exploration to Signoff -    Click for Proceedings
Rita Horner, Sr Director Product Marketing, Synopsys

Chiplet    Packaging Basics -    Click for Proceedings
Roger St Amand, Chief Vice President, Chiplets/FCBGA, Amkor

Chiplet    Integration Basics -    Click for Proceedings
Naran Viswanathan, Signal Integrity Engineer, Intel

Chiplet    Testing Basics -    Click for Proceedings
Jeorge Hurtarte, Sr Director Product Marketing, Teradyne

Pre-Con C: Advanced Packaging Methods (Pre-Conference    Tutorials Track)

Welcome/Introduction
Laura Mirkarimi, VP 3D Technologies, Adeia

Better Sort    Processes Improve Advanced Packaging and Chiplet Manufacturing -    Click for Proceedings
Patrick Pisano, Director Test Strategy, Intel Foundry

Chiplets and    Advanced Packaging Provide Denser, Faster Chips
Adrienne Downey, Market Research Analyst, TechInsights

Implementing    UCIe with Standard and Advanced Packaging
Daniel Lambalot, Sr. Principal Engineer, Alphawave Semi

Rapid &    Unified Manufacturing Services for Next-Generation Devices and Packages
Rozalia Beica, Field CTO, packaging, Rapidus Design Solutions

Next-Gen    Connectivity: Glass-Based Substrate Solutions for Ultra High Bandwidth
Sung Jin Kim, CTO, Absolics

Pre-Con D: Introduction to Die-to-Die Interfaces    (sponsored by Alphawave Semi)) (Pre-Conference Tutorials Track)

Panel Members:

Speaker: Jonathon Evans, Principal Architect,    NVIDIA

Panelist: Randy White, ,    Keysight Technologies

Panelist: Sridhar    Valluru, Principal Product Marketing Manager, Chiplets, Arm

Speaker: Sridhar Valluru,    Principal Product Marketing Manager, Chiplets, Arm

Speaker: Pedro Merlo,    Manager of Strategic Planning, Keysight Technologies

Speaker: Jerome Glisse,    Software Engineer, Google

Speaker: Letizia    Giuliano, VP Solutions Engineering, Alphawave Semi

Panelist: Jonathon Evans,    Principal Architect, NVIDIA

Panelist: Letizia Giuliano,    VP Solutions Engineering, Alphawave Semi

Speaker: Chang-Hyo Yu,    Chief Architect, Rebellions

Panelist: Gerald Pasdast,    Sr Principal Engineer, Intel

Speaker: Gerald Pasdast,    Sr Principal Engineer, Intel

Welcome/Introduction to    Die-to-Die Interfaces - Letizia Giuliano, VP Solutions Engineering,    Alphawave Semi
UCIe Layered Approach to Die-to-Die Interface - Gerald Pasdast,    Sr Principal Engineer, Intel
UCIe Offers Flexible Manageability and Security - Jerome    Glisse, Software Engineer, Google
Die-to-Die Interoperability: Breakthroughs in AI with Chiplets - Sridhar    Valluru, Principal Product Marketing Manager, Chiplets, Arm
Jonathon Evans, Principal Architect, NVIDIA
Developing a Die-to-Die Interface for a Scalable Chiplet Technology    - Chang-Hyo Yu, Chief Architect, Rebellions
Using Golden Die in Interface Testing - Pedro Merlo, Manager of    Strategic Planning, Keysight Technologies
Panel: Choosing the Best Interface for Your Application - Joshua    Rubin, Sr Engineer, IBM Research
Letizia Giuliano, VP Solutions Engineering, Alphawave Semi
Gerald Pasdast, , Intel

Special Event: Ethernet 2025 Workshop (Pre-Conference    Tutorials Track)

Ultra-Low    Latency
David Lariviere, Professor, University of Illinois

Reliability    and Security
Ariel Hendel, , Intel

Chihjen Chang (CJ), SoC Chief    Architect, Intel
Anjali S. Jain, , Awumba
Introduction    to the Ethernet 2025 Workshop
Paul Borrill, Chief Product Officer, Daedaelus

Pre-Con E: Design Methods (sponsored by VeriSilicon)    (Pre-Conference Tutorials Track)

Applying    Digital Twin Technology to Chiplet Development
Andy Heinig, Leader Advanced Packaging Working Group, Fraunhofer IIS

Kevin Yee, Sr. Directory of    Foundry Marketing, Samsung Semiconductor
Jonathan Smith, , Cadence
Modular    Hardware-Assisted Approach to Multi-Die Verification -    Click for Proceedings
Frank Schirrmeister, Executive Director, Strategic Programs, Systems    Solutions, Synopsys

Distributed    Large-Scale AI Systems Use Chiplets with Optical Interconnect
Denis Dutoit, Sr Project Leader, CEA-List

Simplifying    the Use of Co-Packaged Optics with Chiplets
Sylvie Joly, Partnerships Manager 3D integration & packaging, CEA-List

Chiplet    Architecture for Large Capacity CXL Memory Applications
Dongsop Lee, Director, SK hynix

Minsoon Hwang, Director, SK hynix

Pre-Con F: Working with Foundries (Pre-Conference    Tutorials Track)

Panel: Key    Issues in Working with Foundries -    Click for Proceedings
Kevin Yee, Sr. Directory of Foundry Marketing, Samsung Semiconductor

Emmanuel Ollier, Head of    Laboratory, CEA-Leti
Marc Hutner, , Siemens
Engaging    Foundries to Deliver Chiplet-Based SoC's -    Click for Proceedings
Marc Meunier, Director of Ecosystem Development, Arm

Building    Your Chiplets with Foundry! -    Click for Proceedings
Kevin Yee, Sr. Directory of Foundry Marketing, Samsung Semiconductor

Efficient    Integration of Chiplets in a 3DIC R&D Foundry -    Click for Proceedings
Emmanuel Ollier, Head of Laboratory, CEA-Leti

Achieving    On-Time Delivery of Production-Ready Designs -    Click for Proceedings
Marc Hutner, Director of Product Management for Tessent Yield Learning,    Siemens

Pre-Con H: The Open Chiplet Economy Opens its    Marketplace (sponsored by OCP) (Pre-Conference Tutorials Track)

The Open    Chiplet Economy Marketplace Is Open -    Click for Proceedings
Anu Ramamurthy, OCP Project Co-Lead, Open Compute Project

Business    Analysis and Tradeoffs for Chiplet-Based System Design -    Click for Proceedings
Raghu Shankar, , Chiplets Entrepreneur

Steve Helvie, VP Channel    Development, Open Compute Project
Breaking    Down Barriers to Using Chiplets (Panel) -    Click for Proceedings
Cliff Grossner, Chief Innovation Officer, Open Compute Project

Standarized    Metrics for Chiplet Interconnect (PHY) Comparison -    Click for Proceedings
Shahab Ardalan, Co-Founder - Vice President Of Engineering, Enosemi

Imagine a    World with an Abundance of Wires -    Click for Proceedings
Jawad Nasrullah, CEO, Palo Alto Electron

How d-Matrix    Is Leveraging ODSA’s BoWDie-to-DieLink to Transform Generative AI -    Click for Proceedings
Keith Nellis, , d-Matrix

Modularity    for High Performance Computing (HPC) and Artificial intelligence (AI) -    Click for Proceedings
Patricia Gonzalez, Research Scientist, Lawrence Berkeley Laboratory

Business    Analysis and Tradeoffs for Chiplet-Based System Design
Raghu Shankar, , Chiplets Entrepreneur

Steve Helvie, VP Channel    Development, Open Compute Project
BoW PHY 2.1
Elad Alon, CEO, Blue Cheetah

Kevin Donnelly, VP Strategic    Marketing, Eliyan
Kash Johal, , YorChip
Effective    Management of Chiplet IP for Successful Designs -    Click for Proceedings
Vishal Moondhra, VP Solutions, Perforce

Chiplet-based    SiP Testing: Challenges and Solutions -    Click for Proceedings
Aparna Tarde, Product Manager, Synopsys

Rajesh Pendurkar, Director    Silicon Engineering, Capgemini
3D-IC Design    Kits Help Produce Drop-in Chiplets -    Click for Proceedings
David Ratchkov, CEO, Thrace Systems

James Wong, CTO, Palo Alto    Electron

Chiplets: The Key to Solving the AI Energy Gap    (sponsored by Keysight) (Superpanel Track)

Panel Members:

Panelist: Simon Rance, General Manager -    Process and Data Management, Keysight Technologies

Panelist: Paul Borrill,    Chief Product Officer, Daedaelus

Panelist: Frank    Schirrmeister, Executive Director, Strategic Programs, Systems Solutions,    Synopsys

Panelist: Sailesh Kumar,    CEO, Baya Systems

Chat with the Experts (Beer/Pizza Roundtable)    (Pre-Conference Tutorials Track)

Introduction to the 2025 Chiplet Summit (CS 2025    Keynotes Track)

Chairman Welcome -    Click for Proceedings
Charles Sobey, General Chair, Chiplet Summit

Keynote 1: Synopsys (CS 2025 Keynotes Track)

Accelerating AI Chip Development with 3D Multi-Die    Designs -    Click for Proceedings
Abhijeet Chakraborty, VP Engineering, Synopsys

Special Presentation 1: UCIe Consortium (CS 2025    Keynotes Track)

Enabling an Open Chiplet Ecosystem at the Package    Level -    Click for Proceedings
Brian Rea, Marketing WorkGroup Chair, UCIe Consortium

Keynote 2: Alphawave Semi (CS 2025 Keynotes Track)

Scaling Connectivity for Chiplet-Based AI Systems -    Click for Proceedings
Tony Chan Carusone, CTO, Alphawave Semi

Special Presentation 2: Silicon Catalyst (CS 2025    Keynotes Track)

Accelerating Chiplet Startups -    Click for Proceedings
Nick Kepler, COO, Silicon Catalyst

Keynote 3: Arm (CS 2025 Keynotes Track)

Meeting the Challenge of Diverse AI Workloads with    Chiplets -    Click for Proceedings
Eddie Ramirez, VP Marketing - Infrastructure Business Unit,, Arm

Keynote 4: Teradyne (CS 2025 Keynotes Track)

The Right Testing Strategy Can Save Designs -    Click for Proceedings
Nitza Basoco, Technology and Market Strategist, Teradyne

Chiplets: Where We Are Today (sponsored by Applied    Materials) (Plenary Track)

The Chiplet    Market Today and Where We’re Headed -    Click for Proceedings
Jim Handy, Analyst, Objective Analysis

Got a Lot of    Chip Designin' to Do -    Click for Proceedings
Jawad Nasrullah, CEO, Palo Alto Electron

A-101: Security - 1 (Design/Security Track)

Simple    Solution for Certifying Chiplet Origin
Richard Beaudry, CEO, Digitho

Efficiently    Address Side-Channel Leakage Using Pre-Silicon Simulation
Nicole Fern, Principal Security Analyst, Keysight Technologies

Security    Solutions for Multi-Die Designs
Dana Neustadter, Senior Director of Product Management, Synopsys

Multi-Layered    Security for Chiplet Testing
Lee Harrison, Marketing Director, Siemens

B-101: Interfaces - 1 (Interfaces & Integrations    Track)

Chiplet    Interconnect Test and Repair Using Test Standards -    Click for Proceedings
Anshuman Chandra, Lead R&D for 3D/2.5D Devices, Siemens

Martin Keim, Product Manager,    Siemens
Interface IP    Requirements for AI Applications and 3D Packaging Technologies -    Click for Proceedings
Manuel Mota, Sr. Product Manager, Synopsys

C-101: Creating Foundry-Ready Chiplet Designs Panel    (sponsored by Chroma ATE) (Panel Track)

Panel Members:

Panelist: Boris Vaisband, Assistant    Professor, UC Irvine

Panelist: Kenneth Larsen,    Director Product Marketing, Synopsys