moduleclk_div_3(clk, reset, clk_out); input reset,clk; output clk_out; reg clk_out; reg [1:0] cnt; always@(posedge clk or negedge reset) begin if(!reset) begin cnt<=2'b00; clk_out<=0; end else if(cnt==2'b01) begin clk_out<=~clk_out; cnt<=cnt+1'b1; end else if(cnt==2'b10) begin clk_out<=~clk_out; cnt<=2'b00;end else cnt<=cnt+1'b1; end endmodule
占空比1/3
要将一个输入时钟除以3,需要50%的占空比,由verilog hdl编写。
moduleclk_div_3(clk, reset, clk_out); input reset,clk; output clk_out; reg clk_out1, clk_out2; reg [1:0] cnt1,cnt2; assign clk_out = clk_out1 | clk_out2; always@(posedge clk or negedge reset) begin if(!reset) begin cnt1<=2'b00; clk_out1<=0;end elseif(cnt1==2'b01) begin clk_out1<=~clk_out1; cnt1<=cnt1+1'b1; end elseif(cnt1==2'b10) begin clk_out1<=~clk_out1; cnt1<=2'b00;end else cnt1<=cnt1+1'b1; end
always@(negedge clk or negedge reset) begin if(!reset) begin cnt2<=2'b00; clk_out2<=0; end elseif(cnt2==2'b01) begin clk_out2<=~clk_out2; cnt2<=cnt2+1'b1; end elseif(cnt2==2'b10) begin clk_out2<=~clk_out2; cnt2<=2'b00;end else cnt2<=cnt2+1'b1; end endmodule