对高速通信网络和高速计算机日益增长的需求使得设备的集成度以及器件和互连封装密度大大增加。时钟和数据传输速率的增长加剧了电磁效应，这些现象不再是简单的二阶效应，导致了更差的电性能、低噪声抑制和潜在的数据错误，这在数字网络中是非常不希望看到的。随着频率和速度持续增加，信号波长变得与结构尺寸相当，功率分布网络、封装和互连的简化模型必须被更复杂的结构取代。本课程旨在探索高速计算机和通信电路设计中涉及信号完整性分析的技术，包括但不限于：互连集成系统（封装结构、电气信号、时钟分布、趋肤效应、功率波动、寄生效应、噪声抖动、封装层次、多层布线结构….）的功能/要求/限制；互连建模与仿真（瞬态和串扰模拟、非线性电路仿真、封装CAD工具）；提高电源/信号完整性的设计技术。
The ever increasing demand for high speed communication networks and fast computers has resulted into high levels of integration leading to increased packing density of devices and inter-connects. Moreover, the increase in clock and data transmission rates has exacerbated the electromagnetic phenomena which are no longer second-order effects and lead to poor electrical performance, low noise rejection and possible data error which are highly undesirable in digital net-works. As frequency and speed increase, signal wavelengths become comparable to structural dimensions and simplified models for power distribution networks, packages and interconnects must be replaced by more complex structures. This course is designed to explore the signal integrity aspects involved in the design of high-speed computers and communication circuits. Topics to be discussed include but are not limited to: Functions/requirements and limitations of interconnects for system integration (packaging structures, electrical signal and clock distribution, power level fluctuations, skin effect, parasitics, jitter noise, packaging hierarchy, multilayer wiring structures....); Modeling and simulation of interconnects (transients and crosstalk simulations, nonlinear circuit simulation, CAD tools for packaging...);Design techniques for improving power/signal integrity.
