Course title: Phase-locked loops for wireless transceivers
PART I: System and Circuit Design Aspects of PLL
(
Day1)
1. Phase-lock basics tailored for IC designers为IC设计师定制的锁相环基础
1.1. PLL loop dynamics and transient performance锁相环动态特性和瞬态特性
1.2. Basic system parameters系统基本参数
2. System design perspectives系统设计
2.1. Phase noise and jitter相位噪声和抖动
2.2. Spur generation直带(Spur:杂散)
2.3. Settling time建立时间
2.4. Bandwidth optimization频宽优化(带宽优化)
3. Practical circuit design aspects电路设计实操
3.1. Building blocks 组成部分
3.2. Key design aspects关键设计
3.3. Analog vs. digital design模拟和数字设计
4. Digital-intensive PLLs锁相环数字密集型
4.1. DPLL architectures and design issues数字锁相环的结构和设计问题
4.2. Digital PLL with 1-bit TDC一位TDC数字锁相环
4.3. Hybrid PLL混合PLL
PART II: Frequency Synthesis and Modulation in Modern Transceivers现代收发器频率合成和调制
(Day2)
5. Design consideration for frequency synthesizers频率合成的设计考虑
5.1. Phase noise and spur requirements for wireless systems无线系统对相位噪声和杂散要求
5.2. Integer-N vs. fractional-N PLLs
5.3. Analog vs. digital PLLs模拟和数字PLLs
6. Fractional-N frequency synthesizers小数分频频率合成器
6.1. fractional-N PLL
6.2. Quantization noise& spur reduction methods量化噪声和杂散抑制方法
6.3. Nonlinearity & coupling非线性与耦合
7. PLL-based frequency modulation基于锁相环的频率调制
7.1. One-point modulation
7.2. Two-point modulation
7.3. Two+-point modulation